1. Field of the Invention
This invention relates generally to processor-based systems, and, more particularly, to calculating error correction codes for selective data updates in processor-based systems.
2. Description of the Related Art
Processor systems implement various memory elements and are nearly constantly reading, writing, modifying, and/or updating these memory elements during operation. In order for the processor system to operate correctly, the information stored in memory must be accurate and must be conveyed accurately from the memory to the devices that are going to use the information stored in the memory. However, errors can (and inevitably do) creep in and corrupt data stored in the memory. Moreover, transmission errors may corrupt accurate information as it is being transmitted from the memory to other devices within the processor system. Conventional processor systems therefore implement error detection and correction functionality.
Error detection and correction techniques use redundant information to identify corrupted bits and in some cases to restore the value of the bit to its correct value. For example, an additional number of bits can be added to selected blocks of data for the implementation of error correcting codes (ECCs), which may sometimes also be called error correction codes or error correcting circuits. The additional ECC bits contain information about the data that can be used to correct problems encountered while trying to access the real data bits. The ECC bits can be generated by applying logical operations such as XOR to combinations of the data bits that are selected according to a particular error correcting algorithm. When the data bits and the ECC bits are read out of memory, error detection/correction logic can use the data bits and the ECC bits to detect the presence of errors in the data bits and to correct some or all of these errors. For example, the Reed-Solomon algorithm can detect and correct large numbers of missing bits of data and this algorithm requires the least number of extra ECC bits to recover a given number of corrupted data bits.
The latency to compute ECC bits for data stored in a memory has a number of logic levels. For a read-modify-write operation, the data read from the memory is corrected, the data is changed, and then new ECC values are computed before writing the data back to memory. This error correction latency can represent significant and sometimes unnecessary latency and/or processing overhead. For example, many processing devices utilize caches to reduce the average time required to access information stored in a memory. A cache is a smaller and faster memory that stores copies of instructions and/or data from a main memory that are expected to be used relatively frequently, e.g., by a central processing unit (CPU). The cache uses a tag array that indicates the main memory address of the stored copy of the instruction and/or data. The tag array also includes one or more bits to indicate the current state of the information stored in each line in the cache. For example, the tag array may include a valid bit that indicates whether the corresponding line in the cache includes valid data.
Read-modify-write operations are commonly used to perform state updates in a cache memory. For example, a read-modify-write operation can be used to clear the valid bit when a line is invalidated. The read-modify-write operation does not, however, necessarily change any of the other bits in the tag array. For example, the main memory address indicated in the tag array does not change when the status of the line changes. Nevertheless, performing the read-modify-write operation on the tag array requires that all of the ECC bits for the updated line in the tag array be re-computed before writing the data back to memory. The number of state bits in the tag array is typically much smaller than the number of bits that are used to store the main memory addresses. Re-computing all of the ECC bits for every read-modify-write operation performed on the tag array therefore generates unnecessary latency and processing overhead.